The trend with electronic devices is toward smaller sizes and higher speeds. As such devices decrease in size their ability to tolerate higher voltage decreases. For example devices fabricated at scales of 28 nm (nanometers) and below may utilize a ˜35 A (angstrom) oxide thickness and cannot sustain operational voltage stress beyond about 2.0V (volts). Operational voltage stress is stress on the structure and function of a circuit due to voltage levels that exceed the circuit's physical capabilities. Many electronic devices fabricated at lower scales are required to handle voltages higher than 2.0V, i.e. 3.3V, either to remain backward compatible with older devices, or for broad market applicability.
A digital receiver circuit stage is often utilized in electronic devices. This stage performs two functions: (a) to provide noise immunity, and (b) to digitize an analog signal applied on an input signal terminal of the electronic device. A CMOS-technology receiver circuit has an advantageous power, performance, and area characteristics compared to many alternatives. A high speed CMOS receiver circuit fabricated at 28 nm or lower scales may be required to support 3.3V and 1.8V signal voltage levels while retaining power and area efficiency.
One way to enable electronic devices to support higher voltages, i.e. 3.3V, is to utilize electrical components, especially transistors, fabricated with ˜50 A oxide thicknesses. However, this may lead to overall performance loss and a larger circuit on-die area.
FIG. 1 illustrates a conventional receiver circuit 100. The conventional receiver circuit 100 comprises a clamp transistor 102, a Schmitt trigger circuit 104, and a level shifter 106. The conventional receiver circuit 100 is familiar in the art. At a high level, the clamp transistor 102 limits the voltage level of signals applied to later stages of the circuit to safe (non-damaging) values. The Schmitt trigger circuit 104 digitizes the limited analog voltage passed from the clamp transistor 102. The level shifter 106 shifts the output of the Schmitt trigger circuit 104 to logic values (logical “1”s and “0” s) suitable for processing in later stages.
All circuit components of the conventional receiver circuit 100 are 35 A thick oxide devices that can support 1.8V operation (e.g., a low range operational mode) within a tolerance (e.g., +/−10%), for example. The clamp transistor 102 clamps the voltage at input signal terminal (which for example may range from 0-3.3V) to 1.8V to protect the circuitry in later stages from operational voltage stress. The signal passing the clamp transistor 102 is digitized—converted from analog to digital format—by the Schmitt trigger circuit 104. The clamp transistor 102, being an NMOS transistor, clamps the input signal terminal voltage to 1.8V−Vt, where Vt is the threshold voltage drop across MN5. This in turn requires the Schmitt trigger circuit 104 thresholds to be configured at lower values, compromising noise immunity. The input signal voltage level subsequent to MN5 does not have the full voltage range VSSO-VDD18 (the full “rail-to-rail” range) and thus the PMOS transistor device MP1 never turns off (a characteristic of Schmitt trigger circuits of this type). This in turn incurs substantial standby current in the Schmitt trigger circuit 104. Due in part to it's lowered noise immunity, the conventional receiver circuit 100 may not perform well at frequencies beyond a few 10's of megahertz.
To mitigate these problems, the clamp transistor 102 may be replaced by a native NMOS transistor device. A native NMOS transistor is a variety of transistor that is doped such that it's electrical properties are intermediate between enhancement and depletion modes. A native transistor has nearly zero threshold voltage. However, native transistors are up to 2-3 times longer and wider in size than a standard transistor with a threshold voltage drop. Therefore the option of using a native transistor for the clamp transistor 102 may not be practical at smaller fabrication scales.